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Intel announced three new packaging technologies: the future CPU will be like this

via:博客园     time:2019/7/11 17:09:41     readed:263

Author/Editor: Above Q, Source: Fast Technology

Intel proposed a new six strategic pillars last year, in which package also occupied a very important position. Most people are more likely to be more concerned about the xxnm process, knowing little or not too much about the package.

In fact, with the increasing complexity of semiconductor processes, traditional single-chip packages have become increasingly out of date, with performance, power, and cost becoming increasingly disproportionate, especially for high-performance chips.

The third generation of AMD just released, and the upcoming second generation of Snapdragon, is a typical representative of this change. They all use the chiplet chiplet design to separate a single large chip. Different modules. Make different small chips and integrate them together.

Intel has also introduced EMIB 2.5D and Foveros 3D packaging technology. The former is Kaby Lake-G, which integrated Vega GPU core last year. The latter will have Lakefiled at the end of this year, which is 10nm and 22nm.

Yesterday, Intel announcedThree new packaging technologies Co-EMIB, ODI, MDIOThe basic principles areUsing the optimal process to make different IP modules, and then using different packaging methods, high-bandwidth and low-latency communication channels, integrated on a single chip to form a heterogeneous computing platform.

At the scene, Intel also produced a few conceptual samples, which can be seenThere are up to 9 dies on a single substrate, and the size and function are different, and the integration is different.


Co-EMIB is simply a combination of EMIB and Foveros that can interconnect multiple 3D Foveros chips to create larger chips.

An example introduced by Intel consists of four Foveros stacks, each with eight small compute chips connected to the base die through TSV vias, and each Foveros stack connected to two adjacent stacks via Co-EMIB. HBM memory and transceivers are also organized through Co-EMIB.




ODI pays more attention to interconnect technology, and its whole process is “Omni-Directional Interconnect”. Omni-Path is an efficient interconnection method used by Intel in data centers.

As its name stands for Directional,ODI can be interconnected horizontally or vertically, and the vias are larger, so the bandwidth is higher than conventional TSVs, and the resistance and delay are lower. In addition, current can be supplied directly from the package substrate to the die.

It also requires fewer vertical via channels than traditional TSVs.Therefore, the die area can be reduced, and more transistors and higher performance can be accommodated.





MDIO means Multi-Die IO, which is multi-die input and output.An evolution of AIB (Advanced Interconnect Bus) that provides EMIB with a standardized SiP PHY-level interface that interconnects multiple chiplets.

The pin bandwidth has been increased from 2Gbps to 5.4Gbps, the IO voltage has been reduced from 0.9V to 0.5V, and it is claimed to be more advanced than TSMC's recently announced LIPNCON.


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