The theme of the conference was “Difficulty and Escorts Hard Technology Development”, which carried out extensive and in-depth academic exchanges on hard technology in the fields of chips, software and systems, and attracted more than 500 people from academia and industry to participate in the conference. At this conference, we discussed many hot topics in the field of integrated circuits, such as chip security, open source EDA and open source IP, storage fault tolerance and storage computing. The most interested is the work on open source EDA introduced by Dr. Luo Guojie from Peking University. .
In the special invitation report of the conference on August 14th, an open source EDA framework initiated by the country, the OpenBelt initiative, was proposed by the proponent and associate professor Luo Guojie of the Center for Energy Efficiency Computing and Application (CEDA) of Peking University. The design motivation and ideas of OpenBelt are detailed in the report. OpenBelt is an open source EDA framework initiated by Peking University, Institute of Computing Technology of Chinese Academy of Sciences, Tsinghua University, Fudan University and other EDA field research units. The purpose is to build autonomous, innovative and satisfying through the strength of the academic and industrial circles in the EDA field. The new design methodology of the post-Moore era chip design ecology and community.
OpenBelt open source EDA framework
Dr. Luo Guojie's "OpenBELT: Open Source EDA End-to-End Framework" Conference Report
Dr. Luo’s conference report begins with the development of talents with leading technology and mature EDA. With reference to the R&D investment of EDA giants, both Synopsys and Cadence have spent more than RMB 6 billion to RMB 7 billion in research and development in 2018. At least 3,000 R&D engineers are required each year to achieve innovative R&D capabilities similar to those of the giants. However, at present, the training of talents in the domestic EDA field is still quite lagging behind, and the number is seriously insufficient. Dr. Luo made a preliminary estimate in the report: Assume that domestic students account for one-sixth of the submissions of IEEE TCAD in the top EDA journals, that is, about 30 per year, and assume that doctoral students need to send 3 every five years. In the paper, it is estimated that there are only about 50 doctoral students in the field of EDA in China. This is still a big gap compared to the manpower needs. On the one hand, how to effectively cultivate talents in the EDA field to make up for this huge gap is an urgent problem to be solved. At the same time, it also shows that we must develop tools at the same level as the current leading EDA tools based on the existing technology. First, we must solve the problem of insufficient talent reserve.
Figure: Cadence and Synopsys annual R&D expenses (CDNS: Cadence, SNPS: Synopsys)
With reference to recent advances in the Internet and artificial intelligence fields, open source technologies and communities have contributed to the rapid growth of technology in developers and the field. Many of the most popular deep learning libraries are now open source. The general developer community Stack Overflow, GitHub provides a lot of code and problem solutions, the informal technical discussion platform arxiv and quora will also share some preliminary research results and opinions. Open source technologies and communities have lowered the threshold of the field, enabling researchers outside the field to access more cutting-edge, more specific problems and their solutions, and can also make certain contributions to promote the development of the field.
Dr. Luo’s report then analyzes the importance of designing an open source end-to-end EDA toolchain. EDA developereducationAnd the scale of training, the elimination of professional technical communication barriers in an open community, and the absorption of social resources in an end-to-end open source tool chain, which absorbs some government funds in the field of natural sciences and engineering exploration through custom chip development, and facilitates technical needs. The expression and evaluation of technical achievements are delivered to absorb the funds for school-enterprise cooperation, and to reduce the difficulty of small-scale independent entrepreneurship and survival to absorb venture capital.
Of course, unlike traditional software, open source EDA has its own difficulty. EDA skills span a wide range of complex expertise across the algorithmic and physical aspects. Developing a complete EDA tool chain requires the support and maintenance of many community developers, as well as the large amount of high performance required to run large-scale EDA tools.server.
Software complexity issues can be addressed through intelligent, hierarchical, and functional reuse throughout the EDA development process. A complete EDA development process can be divided into the following levels: specific point tools (such as ExtTool, STA, P & R, synthesis, etc.), special solvers (such as DAE solvers, PDE solvers, Machine learning, Compilers, etc.) General solvers (such as nonlinear solvers, Fast linear solvers, Discrete optimization, etc.), and mathematical models (continuous and discrete mathematics). If you can build a high-quality full-process open source EDA algorithm framework through layering and functional reuse, you can target many goals such as ASIC processes, FPGA processes, custom architecture processes, brain-like chip processes, etc., in chip designers, EDA. Algorithm developers and framework developers have established a cooperative system that can be quickly iterated and clearly defined, and work together to solve complex and cumbersome EDA problems.
Figure: Open source EDA algorithm development framework
At present, some frameworks and projects for open source EDA have been proposed abroad. Among them, IEEE CEDA proposed the DATC project, which will organize a set of open source EDA processes according to a certain design standard format by a single point tool in the design automation competition held by the academic community; OpenROAD project funded by the Defense Advanced Research Projects Agency DARPA. Through the research and development of open source EDA tools, to achieve the goal of the intelligent design of the electronic device IDEA, that is, no one is involved in the chip design within 24 hours. At the same time, DARPA's e-revival program related to open source hardware and EDA, such as open source hardware project POSH, IP reuse project CHIPS, domain-specific chip project DSSOC, and software-defined hardware project SDH are also closely related to design methodology innovation. .
Figure: Foreign open source EDA project
In order to attract more developers to join the EDA field, EDA needs to be combined with other emerging fields, which mainly includes three aspects. First, in combination with the upstream of the EDA field, in recent years, emerging devices have brought many special EDA requirements, such as in-bank computing, quantum computing, etc., traditional EDA processes are no longer applicable, which requires developers to design new ones for them. Process. Second, combined with the downstream of the EDA field, there are many emerging applications in recent years, such as the Internet of Things, 5G, AR/VR, etc., which have higher requirements for performance and power consumption. The general EDA process cannot be satisfied. New processes need to be designed for applications; in addition, the EDA design process and design goals need to be adapted to emerging algorithms, and machine learning algorithms are a good example. Third, combined with the development of EDA itself, emerging design methodology, such as agile development, will help improve the EDA process.
Figure: New requirements for open source EDA
Dr. Luo finally expressed OpenBelt as a public domain vision rather than a specific project, and it needed to condense the broad powers of the academic community and the industry to solve the problem. Expect the framework to efficiently implement algorithms and code reuse, version management of point tools and processes, distributed and cloud platform support. At present, the Center for Energy Efficiency Computing and Application of Peking University is carrying out the construction of the initial framework of OpenBelt.
In order to further explore the related technologies of open source EDA and open source IP, CCF Fault Tolerance Conference organized a special forum on the afternoon of the 16th and 17th, and invited many scholars and industry guests to deepen from different perspectives such as AI EDA and open source IP. Exploring the feasibility and specific technical route of open source EDA, guests and viewers have always believed that open source EDA can lower the threshold of EDA, which can make the academic community reduce repetitive work, which is very beneficial to the development of academic circles and even the whole EDA field, but how to encourage and promote open source. Work still needs to have in-depth ideas.
The Secretary General of the CCF Fault Tolerance Committee and the researcher of the Chinese Academy of Sciences, who has been working on dedicated processor chips, is also one of the proponents of OpenBelt. In the forum, he expressed the idea that OpenBelt should be combined with agile development. The primary thing about open source is to help reduce costs. However, in terms of current chip design, design complexity and design cycle are too long, which is more urgently needed. If the current generation of design methodology (DA) solves the problem of large-scale design, it satisfies the need for larger scale and higher operating frequency of general-purpose computing chips; the next-generation design methodology may need to focus on the problem of rapid design. That is to say, the problem of agile development meets the needs of more types of dedicated chips in the ternary era of man-machines, shorter design cycles, and less single-chip manpower investment. At the beginning of the design, the OpenBelt framework can be built on a new design language like Chisel, and the open source intermediate file exchange format is designed, so that the latest achievements in graph computing optimization can be well integrated in the current algorithm and system circles. Design faster, more powerful simulation, synthesis and other tools. At the same time, through the open source, attracting more recent research advances in artificial intelligence, making the entire EDA framework more automated. At the same time, by designing and multiplexing open source IP, the cycle of chip design can be greatly accelerated, and OpenBelt should incorporate this convenient advantage.
To be successful, the open source EDA framework requires the joint efforts of the academic community and the industry. It is not easy. The CCF Fault Tolerance Committee continues to hold activities to promote the domestically-led open source EDA framework.
2019 CCF Integrated Circuit Early Career Award was announced, and Associate Professor Jiang Li of Shanghai Jiaotong University won this award.
Another highlight of the conference was the announcement of this year's CCF IC Early Career Award. The Early Chinese Computer Society CCF Integrated Early Career Award was established for young scholars who have been working for no more than six years to support the early careers of young scholars engaged in integrated circuits. This is the only integrated circuit professional award in the China Computer Society system. The first selection was launched last year, and this year is the second year.
After three rounds of judging by seven international and domestic peer experts, Associate Professor Jiang Li of Shanghai Jiaotong University won the award in recognition of his academic contributions in the field of integrated circuit test fault-tolerant design in the post-Moore era.
Associate Professor Jiang Li has been focusing on integrated circuit testing and circuit fault tolerance technology research. He is the first to propose a three-dimensional chip "pre-binding test" architecture design and optimization method for the high cost of 3D chips, and was introduced into IEEE standard P1838. Aiming at the high failure rate of TSV in 3D IC, it is the first to design an extremely efficient TSV repair architecture and redundant resource sharing technology on adjacent wafers in 3D memory, which refreshes the record of 3D memory repair efficiency.
Photo: Professor Wang Yu, Chairman of the Awards, presided over the award ceremony of Dr. Jiang Li
Moore Elite sponsored the CCF Integrated Circuit Early Career Award for two consecutive years. Talent is the engine of the development of the semiconductor industry. Zhang Jingyang, chairman and CEO of Moore Elite, said that it is crucial for the entire industry to continue to attract outstanding young people like Associate Professor Jiang Li to join the industry and fully realize their personal value. At the same time, through the one-stop chip service platform, it can accelerate the transformation of research and development results and promote the development of the industry. This is also the exploration made by the Moore Elite in the four years since its establishment. It provides chip design services, film packaging and testing services for 1500 chip companies. Talent service and business incubator services, while actively exploring innovative models such as SiP, Chiplet and EDA/IP Cloud to help improve the startup rate, efficiency and success rate of chip innovation. The ultimate goal is to use 1/10 of the funds, 1/10. The time and 1/10 of the team completed the chip product development and put it on the market. The mission of the Moore Elite is to let China have no hard-to-do chips. We are constantly striving to move toward this goal step by step.