Author: Q above
With the outbreak of data, the change of data form, and the emergence of new applications such as AI,5G,IoT Internet of things, autopilot and so on, computing is facing a new demand. We are entering a data-centered, more diversified computing era, the traditional single-factor technology has been unable to keep up with the times.
As a semiconductor giant, the focus and strategic direction of Intel in recent years have also been constantly adjusted, from the early PC as the core, Moore's Law as the guide, gradually to data-centered, and in the face of the future new world of intelligent interconnection, Intel is also making various preparations.
At the end of last year, Intel first proposed six new technology pillars to build a comprehensive vision for the future, in which process technology and packaging are regarded as the bottom and core part, which can be said to be the cornerstone of the five pillars of architecture, memory and storage, interconnection, software and security.
Everyone is familiar with the process technology, XX nanometer can be heard every day, so why can packaging be juxtaposed with it?
In the electronic supply chain, chip packaging is usually very obscure, and few people pay attention to it, but it has been playing a key role in silence. Without it, the chip can not connect and communicate with the outside world efficiently.
With the increasing complexity of semiconductor and chip technology, especially the cooperative work of different chips, the role of advanced packaging technology is becoming more and more prominent, which has become the core factor to promote Moore's law in the new era.
At the same time, packaging is not just about packaging and adding a made chip.
With the advanced basic technology, Intel hopes to achieve the function and performance of SoC single chip by connecting multiple chips and microchips in one package and realizing high-density interconnection with high bandwidth and low power consumption.
Intel, which attaches great importance to advanced packaging technology, also continues to produce new multi-chip packaging (MCP) results. From EMIB the year before last to Foveros, proposed at the beginning of the year to the combination of Co-EMIB,ODI,MDIO, and advanced process technology, it is the most powerful backing of chip architecture designers, and also lays a solid foundation for the future differentiation and evolution of chips.
Recently, Intel has invited a number of senior company and technical experts, includingIntel Group Vice President and General Manager of Packaging Test Technology Development, Academician Babak Sabi,Intel and Joint Director of Technology Development, Ravindranath (Ravi) V. Mahajan,Intel package Research, Chief engineer of component Research, Adel Elsherbini,Intel process and Packaging Division Technical Marketing Director Jason GorssWe also try to do a science popularization for all of you here. We have jointly explained the magic of Intel advanced packaging technology and absolute hard core grade dry goods.
First of all, why Intel attaches so much importance to encapsulation technology and proposes different new styles, the reason is simple.
We know that in the traditional chip design concept, we are trying to integrate different modules into a SoC as much as possible. The integration degree is getting higher and higher. CPU, GPU, memory controller, I/O core and so on are all stuffed together and manufactured by the same process.
When the complexity of chip and technology and the difficulty of process are not high, this concept is very suitable, but with the development of the times, it is more and more difficult to control the technical difficulty, power consumption, cost and so on, so it is necessary to reverse the concept.
You know, today's different chip architectures have different missions, more expertise, forced integration of a process, is not the most appropriate and economic approach, such as the traditional CPU and the new accelerator, their independent work effect is better, in addition, different new IP requirements for the process technology are also. Unlike CPUs, which are naturally as new as possible, I/O units are not sensitive.
So,How to combine these different IP in the most optimal way to achieve the balance of size, performance, interconnection, power consumption, heating, cost and other aspects has become the biggest challenge to packaging technology, which Intel has been trying to solve.
The key or difficult point of the realization of advanced packaging technology is mainly due to the fact that the key point or difficulty of the implementation of advanced packaging technology isLight, compact, high-speed signal, density and spacing reductionIn three aspects, this is exactly what Intel has been trying to overcome.
Next, we'll take a look at the features and advantages of Intel's various advanced packaging technologies one by one.
EMIB is all calledEmbedded Multi-Die Interconnect Bridge, meaningEmbedded multi-bare chip interconnection Bridge
This term may be unfamiliar to you, but the most typical product is Kaby Lake-G, Intel's first integration of AMD Vega GPU graphics core, which is separated from HBM memory and encapsulated by EMIB integration.
EMIB is a high density 2D planar packaging technology, which can flexibly combine different types and processes of chip IP, similar to a loose SoC..
In this encapsulation mode, what plays a central role and connects different bare chips isSilicon intermediate layer (Interposer)It can mix various bare chips flexibly, such as CPU, GPU, HBM display memory, etc. There are no strict requirements for the size of bare chips, and the overall manufacturing is simple, the packaging process is standard, and the cost is very economical.
But it also has some shortcomings, such as the intermediary layer added additional connection steps, easy to affect the performance, and the size of the intermediary layer is also limited, so more suitable for some of the integration of bare pieces, interconnection requirements are not too high products.
2D EMIB can be said to be a new starting point of Intel advanced packaging technology, but the play space of 2D plane is obviously limited, and the application of Foveros 3D stereo packaging is born.
Foveros introduced 3D stacked design for processors for the first time, which is the key technology to greatly enhance multi-core, heterogeneous integrated chips.
Different from the previous simple connection logic chip, memory chip, Foveros innovatively stack different logic chips, connect together, can
In this way, traditional large chips can be decomposed into smaller combinations of small chips. At the same time, different previously dispersed modules can be integrated to meet the design requirements of different applications, power consumption range, shape size, and achieve higher or more appropriate performance at lower cost.
Due to the use of 3 D stacking, the packaging density and integration of Foveros are higher.2D EMIB package bare chip spacing can achieve 55 microns, in the future can only be reduced to 30-45 microns, 3D Foveros can now achieve 50 micron spacing, the future can be further reduced to 20-35 microns (with solder), or even less than 20 microns (without solder).
The first product code name of Foveros package, Lakefield, is manufactured in the latest 10nm process, while integrating 22nm small cores and many expansion units, which will be shipped by the end of this year.
2D EMIB,3D Foveros has its own advantages, and when the two are organically integrated, Co-EMIB, is born.Based on high-density interconnection technology, many 3D Foveros chips can be interconnected through EMIB to produce larger scale chips, which ultimately achieve high bandwidth, low power consumption, and comparatively competitive I/O density. It can also achieve more flexible combination of different chips and modules, basically achieving SoC performance.
More vividly, Co-EMIB package can first implement several different Foveros 3D encapsulation stack modules, each module contains multiple top bare chips, while different bare chips are high speed, closely connected, and the distance between each other is less than 50 microns.
Then, many Foveros 3D modules are connected with other independent bare chips and memory bare chips through EMIB on the basis of a unified package, forming a unified whole.
ODIOmni-Directional InterconnectOmni directional interconnection means Omni-Path is an efficient interconnection method used by Intel in data centers.
The top bare chip can communicate horizontally with other bare chips on the same plane by EMIB interconnection technology, or vertically with the underlying bare chip by using silicon through-hole (TSV) technology in the same way as Foveros, so as to realize all-round interconnection communication.
In addition, the interconnection hole in ODI package is larger, so the bandwidth is lower than the traditional TSV, resistance and delay, the overall performance is better, and the current can be supplied directly from the package substrate to each bare chip to achieve more stable power supply.
ODI packages also require fewer vertical through-hole channels than traditional TSV packages, which release more space for active transistors, thus reducing the area of bare chip, accommodating more transistors and achieving higher performance.
The whole course of MDIO isMulti-Die IOThat is to sayMultiple bare chip input and outputIt is an evolved version of AIB (Advanced Interconnection Bus). It provides EMIB with a standardized SIP PHY interface, which can interconnect multiple small chip combinations.
MDIO package supports the modular system design of small chip IP library, which is more energy efficient, and the response speed and bandwidth density can be more than twice that of AIB technology.
MDIO packaging products will be launched in 2020. Compared with the new products based on the first generation of AIB technology, the bandwidth, density, voltage and energy efficiency indicators have been greatly improved, with pins up to 5.4 GHbps.
It is worth mentioning that TSMC has announced that LIPNCON, a similar packaging technology, will also land next year, with specifications significantly lagging behind except for bandwidth higher than MDIO,.
In addition, in addition to the basic mature chip packaging technology mentioned above,Intel is also looking forward to a variety of new and more efficient packaging interconnection technologies, including high density vertical interconnection for bare chip stacking, full transverse interconnection for large area splicing, no misaligned through holes, and so on.
After all, only by doing well the basic technology of interconnection, can we truly integrate different bare chip modules into an organic whole, and achieve more flexible functions and stronger performance, comparable to SoC single chip.
In addition, after the integration and packaging of multiple small chips, quality testing will become a prominent problem. Intel is also fully aware of this, and will ensure that all technical capabilities and innovative schemes will be adopted to carry out more complete and in-depth test verification, and at the same time, all-round testing will be carried out after the finished product is released to ensure that the expected quality and performance can be achieved.
In today's IC development, test validation is becoming more and more critical.Intel will adopt some internal exclusive verification design rules to complete the test process more efficiently and carry out more open product verification. in addition, because there is no scheme on the market to meet the current needs, new test equipment will be developed internally to further improve the efficiency of test verification.
Power dissipation and heat dissipation is also a key point. Intel also has the corresponding technology and reserves, which can solve the hot spots and hot spots of the integrated package bottom bare sheet, as well as the single chip segmentation technology. At the same time, it will further reduce the heat conduction from the bottom bare sheet to the top bare sheet, and improve the thermal conductivity.
As for cost, we can look at it from a dialectical point of view.If several different modules are integrated and encapsulated in a larger chip, the cost of silicon will be increased, but the cost of encapsulation will be greatly reduced.If all the modules are integrated into a small area of SoC chip, the cost of silicon can be controlled, but the difficulty and cost of packaging are greatly increased.
In the past, I'm afraid not many people have paid attention to packaging technology, let alone its key role in the development of new products in the future. Intel has shown us a new world through its own forward-looking vision and strong technical strength.
On the one hand, different packaging technologies can be used in the most suitable market segments or even customized design.
On the other hand, different packaging technologies are not mutually exclusive, and can even be combined to meet the new needs, just as Co-EMIB is the product of EMIB,Foveros fusion.
In the era of heterogeneous integration, Intel, which has six technological pillars, has undoubtedly overwhelming advantages. In terms of packaging technology alone, Intel also has a holistic and comprehensive solution.
It is worth mentioning that although these packaging technology solutions are exclusive to Intel, there is no plan to open up authorization, but Intel is also trying to promote the establishment of packaging industry standardization, and has had early contacts with two or three industry organizations.
Today, with the development of semiconductor technology, Moore's law can't continue to advance as fast as the traditional trend. But through the hole of the six pillars of technology, Intel has given Moore's law a new meaning and the future is promising.
Finally, we attach some samples of Intel package taken on site. Can you see which packaging technology they correspond to?