On October 7th, Samsung Electronics announced the first to develop 12-layer 3D-TSV (silicon perforation) technology in the industry.
With the expansion of the scale of the integrated circuit, how to plug more transistors within as small an area as possible is a challenge, in which a multi-chip stack package is considered to be the desired star. Samsung said they were able to connect 12 DRAM chips through 60,000 TSVs, and each layer has only 1/20 of the hairline.
The total package thickness is 720
This means that customers do not need to change the internal design to obtain a larger capacity of the chip. At the same time, 3D stacking also helps to shorten the time of data transmission.
Samsung revealed that the HBM memory chip based on 12-layer 3D TSV technology will soon be mass-produced, with a single chip capacity from the current 8GB to 24GB.