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IBM is working on chip "cool techs"

via:博客园     time:2020/1/10 15:32:20     readed:1662

What most readers know most about IBM is their

According to incomplete statistics, flip-chip packaging technology was first introduced by IBM in 1960; single-crystal tube DRAM was first proposed by IBM scientist Robert Dennard; and even the streamlined instruction set now widely used in embedded processors was designed by IBM experts. None of the others, such as SiGe silicon processes, copper interconnections, insulated silicon, strain silicon, and Power processors, has been an innovation that IBM has brought to the semiconductor industry.

Although for a variety of subjective and objective reasons, IBM has gradually lost the power of the past. But from what they've done over the past year,

Let's take a look at the integrated circuits that IBM is working on

Transistor selection after 5 nm: Nanosheet

Recently, the successful trial production of Samsung 3 nm GAA process has spread throughout the author's circle of friends, and has also attracted a wide range of discussion among readers. Because after entering 5 nm, the magic of FinFET is gradually lost, and in order to continuously improve the performance of the transistor, the industry has begun to explore breaking the current from the top of the channel

GAA, which uses a specific material, can wrap the entire current channel into a similar 3D structure, although this design ratio

According to the previous data, Samsung's GAA technology is the result of their cooperation with IBM.

IBM research says the company has been studying gaa transistors for more than a decade and its device architecture has grown from single nanowires to stacked nanosheets. In 2015, IBM researchers published their first nanosheet paper at the S3S conference for the first time

IBM research points out that the company's outstanding equipment architecture utilizes gate all around (GAA) stacked nano chips, so as to solve several challenges faced by FinFET in the real five nanometer (nm) node and later.

Readers who have an understanding of the future development of transistors will surely find that IBM has not used the nanowires discussed before here, but has adopted the nanowires since 2017. To solve this problem, Huiming Bu, director of silicon integration and devices of IBM, mentioned in an interview with IEEE before that, this is mainly related to the advantages that nanowires can bring to pre FinFET. Instead of changing the amount of silicon in a FinFET transistor, which means making some fins longer and others shorter, designers used to increase operating speed or energy efficiency by changing the width of the transistor, he said. However, due to manufacturing constraints, fin silicon must be of the same height, so this is not possible.

to this end, ibm employed nanosheets with a width that can be achieved between 8 and 50 nm. They noted that:

IBM first said the use of these transistors would lead to better computing performance and lower power consumption, mainly because of better electrostatic control and higher package density in the GAA. They say nanosheet provides a better design point for power performance. Compared with the latest and best 7Nm FinFET technology available in the wafer factory, the performance of nanosheet technology is improved by more than 25% at the same power, and the power consumption is saved by more than 50% at the same performance, which is emphasized by IBM.

Secondly, diversified sheets have more simplified design.At the same time, with the help of EUV technology, nanosheet technology can bring a better computer product architecture to AI and 5g era. This enables a more general device design, because devices with different channels of communication can be integrated in the same chip to further optimize power consumption and performance.

Third, good communication control; On the IBM side, increasing the nanosheet stack channel layer can create atomic level controls for channel construction. FinFET can not achieve this precise channel thickness control because it is defined by the combination of lithography and RIE, and its local and global process changes are much higher than the epitaxial thickness changes.

At the earlier IEDM, three IBM researchers, Zhang Jingyun, Ruqiang Bao and Nicolas Loubet, also proposed their solutions for the future development of Nanosheet.

Zhang Jingyun said that due to its excellent electrostatic performance, nano chip GAA devices can achieve extremely high gate length (lmet). In addition to wide sheets, lmet scaling is also critical to meet the needs of high-performance computing. In order to obtain good short channel performance under such a high proportion of lmet, it is very important to control sub fin leakage. IBM researchers, on the other hand, have developed a complete bottom dielectric isolation (BDI) scheme by inserting a dielectric layer under the S / D and gate regions to eliminate the sub channel leakage of scaled lmet. In addition, this function also reduces the parasitic capacitance and provides additional power and performance improvement for the GAA nano chip technology.

TEM cross sections of FinFET and nanosheets

Ruqiang Bao also stressed that in the channel structure of GAA nano chips, due to the existence of sheet to sheet spacing (tsus), the grid region has evolved into 4D. Applications such as HPC also require transistors to control tsus thickness while meeting multiple threshold voltage requirements. And IBM researchers have invented novel processes and integration schemes to achieve multiple dipole thicknesses to achieve volume free multi VT (that is, volume free multi VT), thus realizing very thin tsus. In addition, the researchers invented a method to control the gate boundary during the wide sheet patterning, thus solving a basic problem of nano chip technology.

Nicolas Loubet points out that the unique structural features of the GAA nanosheets technique are formed in the device architecture (InnerSpacer). We have developed a novel isotropic (novel isotropic) dry etching technique for silicon (

In addition, this excellent etching process can be used in the channel release process, providing very low channel thickness changes as well as electrostatic and resistance changes, which is essential to optimize the power / performance of high-performance stacked nano chip devices.

Break through the common bottleneck of von Neumann:In-memory computing

After entering the era of AI, the demand for computing performance of AI tasks is becoming higher and higher, and the traditional architecture of separate computing and storage is facing severe challenges in data exchange and real-time processing because of the limitation of bandwidth. To this end, the industry is exploring a scheme called In Memory Computing, one of which is IBM's phase-change storage (PCM)-based memory scheme.

IBM said that the main advantage of PCM unit is that it can handle most heavy data processing without transferring data to CPU or GPU, so it can achieve faster processing with lower energy consumption. From the introduction, we know that IBM's PCM unit will be used as CPU accelerator, just like Microsoft's field programmable gate array (FPGA) chip to accelerate Bing and enhance its machine learning ability.

According to IBM, its research shows that in some conditions, its PCM chip can run in analog mode to perform computing tasks, and has the same accuracy as the four bit FPGA memory chip, but the energy consumption is reduced by 80 times.

But we should also clearly realize that the disadvantage of analog PCM hardware is that it can not be used for high-precision calculation. Fortunately, both digital CPUs and GPUs can be used. IBM believes that the hybrid architecture can achieve a balance, thus providing faster performance, higher efficiency and accuracy. The design will leave most of the processing to memory, and then transfer the lighter load to CPU for a series of precision correction

In 2017, IBM scientists demonstrated in memory computing solutions for AI applications. IBM research announced that its scientists have proved that unsupervised machine learning algorithms running on a million PCM devices have successfully discovered time correlations in unknown data streams. IBM said that compared with the most advanced classic computers, the prototype technology is expected to increase speed and energy efficiency by 200 times, making it very suitable to support applications in AI for ultra intensive, low-power and large-scale parallel computing systems.

According to reports, the researchers used PCM equipment made of germanium antimony telluride alloy in the test, which was stacked and sandwiched between two electrodes. When scientists apply a small current to a material, they heat it, changing its state from amorphous (with disordered atomic arrangements) to crystalline (with ordered atomic arrangements). IBM researchers have used crystallization kinetics for proper calculations.

From the introduction of IBM, we know that the state of phase-change storage gas can be changed as its name implies by using the unique properties of chalcogenide glass. Chalcogenide glasses have two different physical phases: crystalline phase with high conductivity and amorphous phase with low conductivity. These two phases coexist in the storage element. The conductivity of PCM element can be incrementally modulated by a small electric pulse, which will change the amorphous region in the element.

the total resistance is then determined by the size of the amorphous region, and the atomic arrangement is used to encode information. IBM states:

However, IBM stressed that simulation technology is very suitable for edge AI due to its low power requirements, high energy efficiency and high reliability. Analog accelerator will push the development roadmap of AI hardware acceleration beyond the scope of conventional digital methods. However, although digital AI hardware is competing to reduce the accuracy, so far, simulation has been limited by its relatively low inherent accuracy, which affects the model accuracy. A new technology is developed to compensate for this, which can achieve the highest precision for analog chip.

they were introduced to improve the pcm storage accuracy and stability through a novel method called proj-pcm, which is to insert a non-insulated projection segment at a position parallel to the phase transition segment. In the writing process, the projection segment has the least effect on the operation of the device. however, during reading, the conductance value of the programming state is mainly determined by the projection segment, which is obviously unaffected by the conductance change. this enables the proj-pcm device to achieve higher accuracy than previous pcm devices.

This is what they introduced in 2018 as a phase change memory (PCM) based 8-bit

It is understood that the conductance of the storage material in the box changes with its physical state and can be modified by using an electric pulse. This is how PCM can perform calculations. Because the state can be anywhere in a continuous area between 0 and 1, it is considered one of the reasons for the analog value.

But at the same time, we should also see that the use of PCM and other emerging technologies still brings great challenges. They are vulnerable to noise, resistance drift, asymmetric and nonlinear conductivity changes in response to electrical stimulation, and reliability problems. To solve these problems, IBM researchers from laboratories in Almaden, Yorktown Heights, Tokyo and Zurich have developed new equipment, new algorithms, architecture solutions, novel model training techniques and complete custom designs.

The smallest DRAM unit in the world

According to IBM, DRAM can usually realize the function of main memory due to its excellent storage density and low cost. The high storage density of DRAM comes from the simplicity of its architecture. The storage unit of DRAM is only composed of MOSFET transistor and capacitor.

Although DRAM is the main memory of computer, it is usually not integrated in CPU chip, but exists as an independent chip connected with high-speed bus. We usually use SRAM to make memory on CPU chip (usually called cache). SRAM does not need capacitors and operates at a higher speed than DRAM. The disadvantage of SRAM is its low storage density. However, manufacturing techniques for CPU processing and capacitor formation have become very specialized. That means embedding DRAM in CPU chips is no longer attractive.

IBM says people have been trying to get rid of capacitors over the past two decades, further reducing the size and manufacturing costs of DRAM units. To further reduce the size, the removal of capacitors has almost become a top priority. This requires reducing the lateral size of the cell without reducing the amount of charge that can be stored, leaving a way to make a capacitor

But IBM points out that this is a bottleneck in the long run, not only because of geometric constraints, but also because

This is a single transistor, capacitor free DRAM cell, which uses the transistor body as a capacitor in which the charge (in this case, a hole) is temporarily stored. The injection and extraction of electron holes from the main body of the transistor can adjust the electrostatic behavior of the transistor, resulting in two different current levels. III-V materials such as InGaAs usually have a smaller band gap than silicon, which in principle has the potential to operate at much lower voltages. In turn, this translates into potentially lower power consumption.

IBM convenient said that they have proved the feasibility of a capacitor free msdram cell with a gate length of 14nm. By using the transistor body to store the number of electron holes, we can obtain two different current levels corresponding to binary states 0 and 1. The experimental implementation of the memory concept confirms the results of TCAD simulation.

Compared with the silicon based implementation, IBM's novel concept of InGaAs provides a promising way to realize the active miniaturization of DRAM memory, while reducing the power consumption. The potential for further improvements from the concept of performance metrics (such as retention time), which IBM has struggled to implement with viable strategies.

In fact, the above technology is just the tip of the ice of IBM research project. On the blog of IBM research, they also introduced the development of high-performance photonic devices made of crystal semiconductor gallium phosphide. They said the work represented a breakthrough in the optical processing of semiconductor materials integrated on chips, opening the door to many applications that could have a significant impact on the future of information technology and computing. For example, quantum computer, innovative nonvolatile memory called electrochemical random access memory or ecram for deep learning accelerator, and the first cascadable all-optical transistor that can work at room temperature are the future that IBM researchers are exploring.

I believe that with the efforts of these researchers, the whole industry will find a new way out under the bottleneck.

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